Electronic devices, such as tablets, computers, copiers, digital cameras, smart phones, control systems and automated teller machines, among others, often employ electronic components which leverage chip package assemblies for increased functionality and higher component density. Conventional chip packaging schemes often utilize a plurality of integrated circuit (IC) dice to be mounted to a single package substrate. The IC dice may include memory, logic or other IC devices.
The mask cost associated with new die design at advanced technology nodes (7 nm, 5 nm, 3 nm, etc.) is becoming increasingly expensive due to the increased complexity of lithography and the mask making processes. The cost for designing and tape out of a new custom designed IC die is generally over $100,000, and can easily exceed $3,000,000 (USD). For low volume production, even if this cost is not already prohibitively expense, the high cost of design can significantly reduce the return on investment.
Therefore, a need exists for an improved chip package assembly.